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p; wb_cti_i;
40.input [1:0] wb_bte_i;
41.input wb_clk;
42.input wb_rst;
43.input [31:0] wb_dat_i;
44.input [3:0] wb_sel_i;
45.input wb_we_i;
46.
47.output reg [31:0] wb_dat_o;
48.output reg wb_ack_o;
49.output wb_err_o;
50.output wb_rty_o;
51.
52.reg [addr_width-1:0]Cal_A,Cal_B,Result;
53.reg A_Status,B_Status,R_Status;
54.reg [1:0] stat,nextstat;
55.
56.assign wb_err_o=0;
57.assign wb_rty_o=0;
58.
59.always @(posedge wb_clk)
60. if(wb_rst)
61. stat<=0;
62. else
63. stat<=nextstat;
64.
65.always @(stat,wb_adr_i)
66. case(stat)
67. idle:
68. begin
69. wb_dat_o=0;
70. //wb_ack_o=0;
71. if(wb_stb_i && wb_cyc_i && wb_we_i)
72. begin
73. nextstat=write; 论文网
74. end
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